One or more aspects of the inventive concept relate to a power gating circuit and an electronic system including same.
A System-on-Chip (hereinafter referred to as ‘SoC’) is a technology-intensive semiconductor technique whereby the certain complicated systems having various functions may be integrated into a single “on-chip” system. A SoC typically includes a processor configured to control the system as well as various “intellectual properties” or “IPs” controlled by the processor. Here, the term ‘IP’ denotes one or more circuit(s), logic element(s), and/or combination(s) of same commonly integrated on a semiconductor fabrication layout that implemented the SoC. Programming code may be stored in one or more circuit(s) of the SoC.
Mobile devices including a SoC having multiple IPs operate us battery-supplied power, and therefore must be designed when power conservation in mind. So-called “power-gating” is a technique used to decrease power consumption in certain mobile devices. Power-gating essentially blocks current consumption by an IP when it is not currently in use.
Power-gating may be performed by arranging a plurality of switch cells in each IP and controlling the plurality of switch cells with a control signal. A high fanout net (HFN), a daisy chain method, a fishbone method, and the like may be used to generate the control signal. Among these methods, a final acknowledgement (ACK) signal is difficult to generate when the HFN or the fishbone method is used in contrast with the daisy chain method. Thus, the daisy chain method is commonly used. However, in the daisy chain method, one buffer is typically configured with each switch cell, and thus leakage consumption is high due to the relatively large number of buffers as compared to implementations wherein the HFN is used.